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WO/2022/192832A1 |
Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associa...
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WO/2022/192744A1 |
A charge-domain IMC circuit is disclosed and includes: a cluster of 6T SRAM cells; a chargedomain MAC circuit; and an LBL connected to a bit-line of each of the 6T SRAM cells. The MAC circuit includes: a MOS transistor; an input switch; ...
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WO/2022/191103A1 |
In this memory control method, operations pertaining to writing and erasing are controlled in a memory device (4). The memory device (4) has physical sectors (Ps0, Ps1) provided on p-wells on a silicon substrate (7), the physical sectors...
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WO/2022/190742A1 |
Provided is a method for producing hexagonal strontium ferrite powder capable of both ensuring thermal stability and achieving high-density recording. This method for producing hexagonal strontium ferrite powder includes: dissolving a mi...
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WO/2022/192923A1 |
Aspects of the present disclosure provide a method for calibrating crossbar-based apparatuses. The method includes obtaining output data of a crossbar-based apparatus may include a plurality of cross-point devices with tunable conductanc...
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WO/2022/192049A1 |
A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical "1" step and write logical "0" step in the write operations of sel...
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WO/2022/191446A1 |
A method for highlighting a lyric of a sound source is disclosed. A method for highlighting a lyric according to the present invention comprises the steps of: displaying a lyric of a sound source by a user terminal; receiving an input of...
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WO/2022/188085A1 |
Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of ...
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WO/2022/191863A1 |
An erase operation for data memory cells is integrated with a process for detecting dummy memory cells and/or select gate transistors which have an out-of-range threshold voltage. In one aspect, an erase operation is performed for the da...
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WO/2022/189772A1 |
Methods, system and devices for the production of audio records are provided. A record format is selected, and this selection is used to modify a set of digital audio files (31). A music production interface 5 may be provided to receive ...
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WO/2022/188019A1 |
The present disclosure provides a shift register, comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and an impedance transistor, wherein a first pole of the...
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WO/2022/190513A1 |
The present invention prevents errors caused by a rewrite exceeding an upper limit of a memory even if a limit of a number of rewrites of the memory cannot be estimated. A R/W (1) comprises: a memory region management unit (13) that desi...
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WO/2022/188018A1 |
A shift register circuit (100), comprising: an input circuit (110), a reset circuit (180), a first control circuit (120), a second control circuit (130), a third control circuit (140), a fourth control circuit (150), a fifth control circ...
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WO/2022/192883A1 |
A method of generating a modified video file using one or more processors is disclosed. The method comprises detecting objects that are represented in an original video file using computer vision object-detection techniques, determining ...
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WO/2022/191864A1 |
A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper...
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WO/2022/189300A1 |
A device includes an electronic component, and the electronic component includes a first pad, a second pad, and a strip connecting the first pad and the second pad. The device further includes a first electrode in contact with the first ...
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WO/2022/188674A1 |
Disclosed in the present application are a data erasure verification method for a three-dimensional nonvolatile memory, a data erasure method for the three-dimensional nonvolatile memory, and the three-dimensional nonvolatile memory. The...
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WO/2022/191904A1 |
An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may f...
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WO/2022/188176A1 |
Provided in the present application are a storage device and a power supply control method therefor, and an electronic device, relating to the technical field of electronics, and being used for solving the problem in the prior art of rea...
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WO/2022/192784A1 |
An electro-optic random-access memory enables (1) ultra-fast write and read operation (2) featuring differential sensing (3) wavelength, and polarization multiplex high bandwidth memory access (4) enables very large-scale memory array fo...
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WO/2022/190928A1 |
This servo pattern recording method determines a first servo band group constituted from three or more servo bands for recording a servo pattern in which first servo band identification information comprising a plurality of bits is embed...
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WO/2022/188057A1 |
3D memory devices and methods for operating the 3D memory devices are provided. In an example, a 3D memory device (100) includes a plurality of memory layers and a dummy memory layer between the plurality of memory layers and a NAND memo...
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WO/2022/184642A1 |
It is the objective of the present invention to provide a method to increase the readout speed of the information encoded on magnetic storage media using contactless circularly polarized X-rays, allowing real-time, high-fidelity readout....
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WO/2022/187779A1 |
Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a tr...
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WO/2022/186845A1 |
Apparatuses and techniques are described for avoiding current consumption peaks during a program operation for a memory device. The timing of scan operations of latches is adjusted to avoid overlapping with an increase in word line volta...
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WO/2022/186117A1 |
Provided is an optical recording medium which can shorten takt time.　The optical recording medium includes at least one layer of a recording layer. The recording layer comprises an oxide of Bi.
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WO/2022/183649A1 |
The present application provides a fuse fault repair circuit, comprising a fuse array, a signal storage module and a scanning and repair module. The fuse array includes a redundant fuse array and a non-redundant fuse array, and when ther...
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WO/2022/185143A1 |
Provided is a highly reliable semiconductor device. The present invention relates to a shift register circuit including sequential circuits of a plurality of stages. An output signal of a sequential circuit is input to the sequential cir...
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WO/2022/185892A1 |
This magnetic disk drive is provided with a plurality of magnetic disks 30 having the shape of a disk, spacers 80, a hub 90, and a clamp 70. The magnetic disk 30 has a through hole at a central part thereof. The spacer 80 is disposed bet...
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WO/2022/186846A1 |
Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation applies a staircase or multi-level word line voltage concurrent with a fixed level erase pulse to provide mul...
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WO/2022/183314A1 |
A memory. The memory comprises: a cell array comprising multiple storage cells; and multiple circuit units respectively connected to at least one storage cell; wherein each circuit unit is used for: receiving a first bit value of externa...
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WO/2022/187727A1 |
An error sampler circuit (110) includes a differential input voltage input (110A, HOB), a differential reference voltage input (HOE, HOF), a master latch circuit (202), and a slave latch circuit. The master latch circuit (202) includes a...
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WO/2022/186865A1 |
A memory device can comprise an array of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers, and a plurality of ver...
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WO/2022/185090A1 |
The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, ...
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WO/2022/187780A1 |
Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a tr...
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WO/2022/185540A1 |
This memory device comprises a page composed of a plurality of memory cells arranged in rows on a substrate, and performs: a page writing operation for controlling the voltage applied to a first gate conductor layer, a second gate conduc...
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WO/2022/185088A1 |
The present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data...
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WO/2022/186540A1 |
An electronic device according to various examples comprises a microphone, a memory, and a processor. The memory may store instructions which, during a recording operation using the microphone, enable the processor to: duplicate a signal...
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WO/2022/183643A1 |
A processing method and processing apparatus for an out-of-control behavior in a semiconductor manufacturing process. The process method for an out-of-control behavior in a semiconductor manufacturing process comprises the steps of: esta...
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WO/2022/186459A1 |
Disclosed is a point-of-sale management apparatus. The point-of-sale management apparatus comprises: a lens unit which acquires a face image of a customer; a voice recognition unit which recognizes speech uttered between the customer and...
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WO/2022/183951A1 |
A memory array with memory cells may have one or more heaters integrated into the memory array between the memory cells. A processor in communication with the heater may notify the heater to activate when a trigger event occurs.
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WO/2022/183465A1 |
A memory apparatus includes a plurality of memory cells stored with memory data in N dies. Each of the N dies includes M planes. Each of the M planes includes a memory block. The apparatus also includes a controller configured to determi...
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WO/2022/185091A1 |
The present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data...
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WO/2022/185089A1 |
The present disclosure relates to a method comprising the steps of defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum Error Correction Code (ECC) correction ca...
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WO/2022/186393A1 |
Provided is a glass for a magnetic recording medium substrate or for a glass spacer to be used in a magnetic recording/reproducing device that is an amorphous glass that includes at least Li2O, and has a total content of Na2O and K2O of ...
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WO/2022/187009A1 |
A CAM array of compare memory cell circuits includes a decode column corresponding to each set, and each set includes at least one row of the compare memory cell circuits. Each decode column receives a set clock signal addressing the cor...
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WO/2022/182926A1 |
Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrat...
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WO/2022/182374A1 |
A method for reading a flash memory device includes storing configuration files of reliability-state Classification Neural Network (CNN) models and Regression Neural Network (RNN) inference models, and storing reliability-state tags corr...
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WO/2022/181507A1 |
A control device (103) for memory included in a device for realizing a stochastic computing calculating mechanism is provided with: a write interface (11) into which a spike train is input; a read interface (12) which outputs the spike t...
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WO/2022/180905A1 |
A data recording system (2) is equipped with a first removable storage (14) and a second removable storage (16) which can be removed, and a controller (18) for controlling the writing of image data to the first removable storage (14) and...
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