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WO/2022/242371A1 |
In an approach, a processor determines that an inactive data area is present at end-of-tape (EOT) of a tape. A processor, responsive to determining that the inactive data area is present at EOT, securely erases the inactive data area tha...
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WO/2022/244281A1 |
This semiconductor memory device comprises a first memory cell and a second memory cell. In addition, this semiconductor memory device is configured to be able to execute: a first operation, that is, a read operation, a write operation, ...
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WO/2022/246450A1 |
Systems and methods are described that include causing a recording to begin capturing video content. The video content may include a presenter video stream, a screencast video stream, and an annotation video stream. The systems and metho...
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WO/2022/245527A1 |
A data storage device including, in one implementation, a non-volatile memory device having a memory block including a number of memory dies, and a controller coupled to the nonvolatile memory device. The controller is configured to moni...
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WO/2022/243279A1 |
A method (50) for fabricating an asymmetric SOT-MRAM memory cell unit, said memory cell unit comprising a conductor track and a pad, arranged on the conductor track and comprising at least one first magnetic region with free magnetizatio...
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WO/2022/241735A1 |
Provided in the embodiments of the present disclosure are a spin logic device, a processing in-memory device, a half adder and a full adder. In the spin logic device, a magnetic unit comprises a spin Hall effect layer and a ferromagnetic...
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WO/2022/244429A1 |
A nonlinear light absorption material in one embodiment of the present disclosure has nonlinear light absorption properties in a wavelength of 390-420 nm, and comprises, as a main component, at least one compound selected from the group ...
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WO/2022/245383A1 |
Numerous embodiments are disclosed of a non-volatile memory cell array formed in a p-well, which is formed in a deep n-well, which is formed in a p-substrate. During an erase operation, a negative voltage is applied to the p-well, which ...
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WO/2022/244617A1 |
Provided is a method for producing a resin member for a production process of electronic devices which makes it possible to suppress, for a long period of time, adhesion of an adhering substance on a surface. A method for producing a res...
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WO/2022/244611A1 |
A light-absorbing material according to one embodiment of the present disclosure comprises a compound represented by formula (1) as a main component. In formula (1), each of R1 to R14 contains, independently from one another, at least on...
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WO/2022/241652A1 |
Apparatuses, systems, and techniques to detect faults in processing pipelines are described. One accelerator circuit includes a fixed-function circuit that performs an operation corresponding to a layer of a neural network. The fixed-fun...
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WO/2022/241796A1 |
Provided in the embodiments of the present application are a ferroelectric memory and a control method therefor, and an electronic device including the ferroelectric memory. The method is mainly used for improving the storage density of ...
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WO/2022/244430A1 |
A nonlinear light absorbing material according to one embodiment of the present disclosure contains, as a main component, a compound that is represented by formula (1). In formula (1), each of R1 to R6 independently represents a hydroc...
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WO/2022/243458A1 |
Spin Texture Storage Device The present invention relates to a spin texture storage device (100) comprising a closed-loop storage track (110) comprising electric conductive and ferromagnetic material and having a track length, a track wi...
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WO/2022/244431A1 |
The nonlinear light absorption material according to one embodiment of the present disclosure contains, as a main component, a compound represented by formula (1). In formula (1), R1 to R10 are each independently a hydrogen atom, a hal...
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WO/2022/241731A1 |
Provided are a memory chip, a circuit component, an electronic device, and a method for controlling a memory chip. A memory chip (220-11) comprises a reset pin (204), a plurality of command address pins (202), a memory unit (240), and a ...
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WO/2022/239935A1 |
A method for analyzing DRAM performance using row hammering comprises the steps of: performing row hammering to activate, for a preset tRAS time, word lines of a first cell in DRAM, and precharge, for a preset tRP time, the word lines; d...
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WO/2022/240459A1 |
Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memor...
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WO/2022/236491A1 |
Disclosed in the present invention are an automatic pressure relief valve, and a data disaster backup storage device comprising same. The automatic pressure relief valve comprises a valve body, a movable member and an elastic member. The...
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WO/2022/240487A1 |
Various implementations described herein may refer to' a compliance platform.for' use with identity7 data. In one implementation, a method may include receiving a compliance data package from a user, where the compliance data package inc...
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WO/2022/236467A1 |
An input/output module and a memory, used for shortening the data write time and improving the data write efficiency of the memory. The input/output module is coupled to a storage array. The input/output module comprises a drive circuit ...
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WO/2022/237039A1 |
The present invention relates to an SRAM cell suitable for high-speed content addressing and in-memory Boolean logic computing. The SRAM cell consists of a standard 6T-SRAM and two additional PMOS access transistors, read word lines of t...
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WO/2022/240412A1 |
System and method to compress multiple videos are provided, the system includes a video retrieve module configured to retrieve videos from a video library database; a video selection module configured to select videos by a user upon view...
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WO/2022/239194A1 |
According to the present invention, an N+ layer 3a that is connected to a source line SL, a first Si column 2a that stands in the vertical direction, and a second Si column 2b that is on top of the first Si column 2a are arranged on a su...
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WO/2022/236883A1 |
Provided in the present application are a GOA circuit, and a liquid crystal panel and a driving method therefor. The GOA circuit comprises a plurality of cascaded GOA structure units, wherein each stage of GOA structure unit comprises a ...
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WO/2022/241044A1 |
A system and method for measuring the degradation of one or more memory devices of a memory sub-system. An example system including a memory controller operatively coupled with a memory device and configured to perform operations compris...
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WO/2022/236946A1 |
In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plur...
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WO/2022/239228A1 |
This memory device is provided with a page made from multiple memory cells arranged in columns on a substrate. The memory device performs: a page write operation for holding a hole group, which is formed by an impact ionization phenomeno...
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WO/2022/239237A1 |
In the present invention, a N+ layer 3a, a first Si matrix 2 composed of a first Si matrix 2a and a second Si matrix 2b, and a N+ layer 3b are disposed in parallel with a substrate 1 and are connected with each other. A first gate insula...
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WO/2022/239102A1 |
This memory device, on a substrate 1, is provided with: a N+ layer 3a connected to a source line SL and a N+ layer 3b connected to a bit line BL, the layers 3a, 3b being located at both ends of a Si pillar 2 standing in a vertical direct...
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WO/2022/238935A1 |
An electronic device is provided for control of playback based on image capture. The electronic device includes circuitry. The circuitry is communicatively coupled to an imaging apparatus and a rendering device that plays content. The ci...
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WO/2022/237617A1 |
The present disclosure relates to a gating device and a storage array. The gating device comprises: a substrate that is prepared on the basis of a two-dimensional material; and a gating tube that is arranged on the substrate, wherein the...
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WO/2022/239956A1 |
Disclosed is an improved method for operating a program of a three-dimensional flash memory. A program voltage has a value obtained by adding a step voltage to a previous program voltage applied in a previous program operation, and the s...
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WO/2022/239193A1 |
This memory device is provided with a page comprising multiple memory cells arranged in columns on a substrate. The memory device carries out: a page write operation for holding, inside a channel semiconductor layer, a hole group formed ...
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WO/2022/241021A1 |
A disclosed system may include (1) a memory package having a physical memory and optical circuitry, (2) a processor package, separate and distinct from the memory package, having at least one physical processor and additional optical cir...
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WO/2022/239681A1 |
A memory cell (C1) extends in the Y-direction and comprises a power supply wire (11) for supplying a power supply voltage VSS. A well tap cell (C2) comprises: a power supply wire (111, 212) extending in the Y-direction and electrically c...
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WO/2022/239198A1 |
The method of the present invention comprises the steps of: forming, on a substrate 20, an Si pillar 26 comprising an N+ layer 21a connected to a source line SL, a P+ layer 22a that is vertically upright and located in the center, and a ...
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WO/2022/239099A1 |
According to the present invention, first Si columns 22aa to 22da are arranged on an N+ layer 21 that is connected to a source line SL on a substrate 20. The Si columns 22aa to 22da are surrounded; and the distance Lg1 between facing int...
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WO/2022/240497A1 |
Apparatuses and methods can be related to implementing a binary neural network in memory. A binary neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be ...
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WO/2022/239199A1 |
This memory device comprises pages including a plurality of memory cells arranged in columns on a substrate, and performs: a page writing operation of retaining a hole group, generated by impact ionization or gate-induced drain leakage c...
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WO/2022/240454A1 |
A bonded assembly of a memory die and a logic die is provided. The memory die includes a memory array, a plurality of bit lines, and memory-side bit-line-connection bonding pads. The logic die includes sense amplifiers located in a sense...
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WO/2022/239100A1 |
This memory device is provided with a page comprising a plurality of memory cells arranged in columns on a substrate. The memory device carries out: a page write operation for controlling the voltage applied to a first gate conductor lay...
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WO/2022/238798A1 |
The present invention provides a semiconductor device which has a novel configuration. This semiconductor device comprises: a first substrate which is provided with a first peripheral circuit that has a function of driving a first memory...
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WO/2022/239623A1 |
A non-volatile memory device (100) comprises: a memory cell (11A, 11B) that in an initial state stores storage data of a first logical value, and after a program operation has been executed, stores storage data of a second logical value;...
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WO/2022/240591A1 |
A regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, wherein a gate of...
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WO/2022/240896A1 |
A system and method for optimizing a memory sub-system to compensate for memory device degradation. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising:...
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WO/2022/239196A1 |
A memory device according to the present invention is provided with a page comprising a plurality of memory cells that are arranged in a line on a substrate. The present invention carries out the following: a page writing operation that,...
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WO/2022/239192A1 |
According to the present invention, an N+ layer 3a that is connected to a source line SL, a first Si column 2a that is a P+ layer, and a second Si column 2b that is a P layer are arranged on a substrate 1, the Si columns standing in the ...
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WO/2022/235881A1 |
A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a firs...
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WO/2022/233993A1 |
The present disclosure relates to a burst access memory comprising a memory array comprising a plurality of memory macros, each memory macro comprising an array of memory cells arranged in rows and columns, wherein the memory cells in ea...
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