Title:
試験装置および試験方法
Document Type and Number:
Japanese Patent JP2005533250
Kind Code:
A
Abstract:
A test system for testing an electronic device is deployable in two basic configurations. In one of the configurations, a load board (62) that receives a unit (60) of the device is directly attached to a test head (16). In the other configuration, the same load board or one having largely the same pattern of test-head signal transmission positions is coupled through an interface apparatus (66) to a test head. A probe system (64) contacts that load board or/and the interface apparatus. The interface apparatus is normally configured to largely prevent test-head vibrations from being transferred to the probe system. Additionally or alternatively, the load board is vacuum attached to the interface apparatus.
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Inventors:
Soak, Frank M.
Wells, Gary A.
Ho, Thomas P.
Wells, Gary A.
Ho, Thomas P.
Application Number:
JP2004521467A
Publication Date:
November 04, 2005
Filing Date:
June 17, 2003
Export Citation:
Assignee:
Credence systems corporation
International Classes:
G01R31/26; G01R31/28; G01R31/302; H01L21/66; (IPC1-7): G01R31/302; G01R31/26; H01L21/66
Attorney, Agent or Firm:
Shin Uchihara