イベント型試験システム用イベントパイプライン・サミング方法および装置

Title:

イベント型試験システム用イベントパイプライン・サミング方法および装置

Document Type and Number:

Japanese Patent JP2005533253

Kind Code:

A

Abstract:

An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a function for detecting a window strobe request and generating a window strobe enable.

Inventors:

Gomez, Glen
Lee, Anthony

Application Number:

JP2004521858A

Publication Date:

November 04, 2005

Filing Date:

July 12, 2003

Export Citation:

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Assignee:

Advantest Corporation

International Classes:

G01N31/00; G01R31/319; G01R31/3183; G01R31/3193; G06F11/22; G06F19/00; (IPC1-7): G01R31/3183; G06F11/22

Attorney, Agent or Firm:

Kihei Watanabe

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