Title:
有用層で被覆された一対の基板の同時製造方法
Document Type and Number:
Japanese Patent JP2006527478
Kind Code:
A
Abstract:
A method for producing a semiconductor structure that includes at least one useful layer on a substrate. This method includes providing a source substrate with a zone of weakness therein that defines a relatively thick useful layer between the zone of weakness and a front face of the source substrate; bonding the front face of the source substrate to a support substrate and detaching the useful layer from the source substrate at the zone of weakness to transfer the useful layer to the support substrate; implanting atomic species into a free face of the useful layer to a controlled mean implantation depth therein to form a zone of weakness within the useful layer that defines front and rear useful layers, with the rear useful layer contacting the source substrate and the front useful layer containing a greater concentration of defects; bonding a stiffening substrate to the free face of the front useful layer after implantation of the atomic species; and detaching the front useful layer from the rear useful layer along the zone of weakness to form a semiconductor structure comprising the support substrate and the rear useful layer thereon. The structures obtained can be used in the fields of electronics, optoelectronics or optics.
Inventors:
Gisern, Bruno
Ornette, Cecil
Batayo, Benuwa
Muzzle, Carlo
Morrisho, Uber
Ornette, Cecil
Batayo, Benuwa
Muzzle, Carlo
Morrisho, Uber
Application Number:
JP2006508351A
Publication Date:
November 30, 2006
Filing Date:
June 03, 2004
Export Citation:
Assignee:
S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
International Classes:
H01L21/02; H01L21/265; H01L21/762; H01L27/12
Domestic Patent References:
| JPH10135500A | 1998-05-22 | |||
| JPH10326883A | 1998-12-08 | |||
| JP2001210810A | 2001-08-03 |
Foreign References:
| US20020068418A1 | 2002-06-06 | |||
| US6150239A | 2000-11-21 |
Attorney, Agent or Firm:
Tadashi Hanamura
Tadashi Sato
Toshiya Sato
Tadashi Sato
Toshiya Sato