Title:
減少されたゲート高さを有するトランジスタを製造する方法
Document Type and Number:
Japanese Patent JP2007513489
Kind Code:
A
Abstract:
Disclosed is a method and system of forming an integrated circuit transistor having a reduced gate height that forms a laminated structure having a substrate, a gate conductor above the substrate, and at least one sacrificial layer above the gate conductor. The process patterns the laminated structure into at least one gate stack extending from the substrate, forms spacers adjacent to the gate stack, dopes regions of the substrate not protected by the spacers to form source and drain regions adjacent the gate stack, and removes the spacers and the sacrificial layer.
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Inventors:
Park, Heem Young
Agnero, Paul, Dee
Gilbert, Percy, Bee
Lee, Byung, H
O'Neill, Patricia, A
Shahidi, Guha Bam, Gee
Welser, Jeffrey, Jay
Agnero, Paul, Dee
Gilbert, Percy, Bee
Lee, Byung, H
O'Neill, Patricia, A
Shahidi, Guha Bam, Gee
Welser, Jeffrey, Jay
Application Number:
JP2006524629A
Publication Date:
May 24, 2007
Filing Date:
June 29, 2004
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L29/786; H01L21/265; H01L21/336; H01L21/84; H01L27/12; H01L29/423; H01L29/49; H01L29/78; H01L29/45
Domestic Patent References:
| JP2001168323A | 2001-06-22 | |||
| JPH08125175A | 1996-05-17 | |||
| JPH01278777A | 1989-11-09 |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Takeshi Ueno
Tasaichi Tanae