Title:
電源レベルを監視するためのシステムと方法
Document Type and Number:
Japanese Patent JP2008547366
Kind Code:
A
Abstract:
A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.
Inventors:
Lee, Gabriel M
Richmond, Greg Jay
Richmond, Greg Jay
Application Number:
JP2008516911A
Publication Date:
December 25, 2008
Filing Date:
June 01, 2006
Export Citation:
Assignee:
CYPRESS SEMICONDUCTOR CORPORATION
International Classes:
H02J1/00; G05F1/10; H02M1/00
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Shigeki Yamakawa