Title:
電源の完全性を監視するための回路と方法
Document Type and Number:
Japanese Patent JP2008547367
Kind Code:
A
Abstract:
Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described herein provides exemplary steps for monitoring a level of a power supply voltage supplied to one or more system components. A second method describes exemplary steps for monitoring an electrical connection between the power supply (or ground supply) and one or more supply pins. Each of the methods involves monitoring a state of one or more bits stored, e.g., within a status register. The methods may be used separately, or in conjunction with one another, for detecting the occurrence of a power abnormality.
Inventors:
Lee, Gabriel M
Richmond, Greg Jay
Richmond, Greg Jay
Application Number:
JP2008516916A
Publication Date:
December 25, 2008
Filing Date:
June 15, 2006
Export Citation:
Assignee:
CYPRESS SEMICONDUCTOR CORPORATION
International Classes:
H02J1/00; H02M1/00
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Shigeki Yamakawa