Title:
論理エラー保護のためのハイブリッド冗長性を備えたプロセッサ
Document Type and Number:
Japanese Patent JP2011509490
Kind Code:
A
Abstract:
A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units and may consecutively dispatch a same floating-point instruction stream to a floating-point unit. The integer execution units may operate in lock-step such that during each clock cycle, each respective integer execution unit executes the same integer instruction. The floating-point unit may execute the same floating-point instruction stream twice. Prior to the integer instructions retiring, compare logic may detect a mismatch between execution results from each of the integer execution units. In addition, prior to the results of the floating-point instruction stream transferring out of the floating-point unit, the compare logic may also detect a mismatch between results of execution of each consecutive floating-point instruction stream. Further, in response to detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.
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Inventors:
Michael G. Butler
Nonquachi
Nonquachi
Application Number:
JP2010542273A
Publication Date:
March 24, 2011
Filing Date:
January 09, 2009
Export Citation:
Assignee:
Global Foundries, Inc.
International Classes:
G06F11/18
Attorney, Agent or Firm:
Yuji Hayakawa
Ryota Sano
Keisuke Murasame
Ryota Sano
Keisuke Murasame