Title:
半導体デバイスの同時試験のためのシステム
Document Type and Number:
Japanese Patent JP2013531779
Kind Code:
A
Abstract:
A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time.
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Inventors:
Van, Wagenen Bethany
Edward, Sen Jay.
Edward, Sen Jay.
Application Number:
JP2013509224A
Publication Date:
August 08, 2013
Filing Date:
May 04, 2011
Export Citation:
Assignee:
Teradyne, Inc.
International Classes:
G01R31/28
Domestic Patent References:
| JP2007528993A | 2007-10-18 | |||
| JP2007010662A | 2007-01-18 | |||
| JP2004061509A | 2004-02-26 | |||
| JP2004117352A | 2004-04-15 | |||
| JP2010107230A | 2010-05-13 | |||
| JP2003172771A | 2003-06-20 | |||
| JP2007248385A | 2007-09-27 | |||
| JP2010002315A | 2010-01-07 |
Attorney, Agent or Firm:
Hidekazu Miyoshi
Masakazu Ito
Yuko Hara
Masakazu Ito
Yuko Hara