Title:
FAILURE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JP2018155634
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a failure detection circuit capable of detecting a failure of a test mode signal while detecting a failure on own failure detection circuit.SOLUTION: The failure detection circuit includes: a monitor signal generation circuit 1 configured to generate a monitor signal used for failure detection of plural test mode signals which are input each of plural modules 100; a cascade connection circuit 2 including plural OR circuits 21 configured to detect a failure of each of the test mode signals; and a comparison circuit 3 configured to compare an output signal from the cascade connect circuit 2 with the monitor signal to determine existence/absence of failure. The cascade connection circuit 2 includes plural OR circuits 21 which are cascade-connected to each other, and a monitor signal is input to the OR circuit 21a of the first step.SELECTED DRAWING: Figure 1
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Inventors:
FUJIMORI MASAFUMI
Application Number:
JP2017053381A
Publication Date:
October 04, 2018
Filing Date:
March 17, 2017
Export Citation:
Assignee:
TOSHIBA CORP
TOSHIBA ELECTRONIC DEVICES & STORAGE CORP
TOSHIBA ELECTRONIC DEVICES & STORAGE CORP
International Classes:
G01R31/3185; G01R31/28; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Susumu Ito
Yasushi Hasegawa
Osamu Shinoura
Yasushi Hasegawa
Osamu Shinoura