Title:
SEMICONDUCTOR IC BUILT-IN SUBSTRATE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2018195742
Kind Code:
A
Abstract:
To provide a semiconductor IC built-in substrate in which wiring can be disposed in a rear face portion of a semiconductor IC and a void is prevented from being generated between a die attach material and an insulation layer.SOLUTION: A semiconductor IC built-in substrate comprises: a wiring layer 21 which is embedded in an insulation layer 11 and of which an upper surface 21a constitutes the same plane as an upper surface 11a of the insulation layer 11; a semiconductor IC 40 which is disposed on the upper surface 21a of the wiring layer 21 via a die attach film 41; and an insulation layer 12 which is laminated on the upper surface 21a of the wiring layer 21 in such a manner that the semiconductor IC 40 is embedded therein. A rear face 41a of the die attach film 41 is brought into contact with both the upper surface 11a of the insulation layer 11 and the upper surface 21a of the wiring layer 21. Thus, since the wiring layer 21 and the insulation layer 11 configure the same plane, no void is generated between the die attach film 41 and the insulation layer 11. Further, the wiring layer 21 that is positioned in a rear face portion of the semiconductor IC 40 can be effectively utilized.SELECTED DRAWING: Figure 1
Inventors:
TSUYUTANI KAZUTOSHI
KATSUMATA MASASHI
KATSUMATA MASASHI
Application Number:
JP2017099420A
Publication Date:
December 06, 2018
Filing Date:
May 19, 2017
Export Citation:
Assignee:
TDK CORP
International Classes:
H05K3/46
Domestic Patent References:
| JP2011165741A | 2011-08-25 | |||
| JP2004179288A | 2004-06-24 | |||
| JP2005322769A | 2005-11-17 |
Foreign References:
| WO2010010910A1 | 2010-01-28 |
Attorney, Agent or Firm:
Mitsuhiro Washito
Ogata Japanese
Yasuyuki Kurose
Ogata Japanese
Yasuyuki Kurose