Title:
【発明の名称】2段アドレス・デコ―ダ回路
Document Type and Number:
Japanese Patent JP2539924
Kind Code:
B2
Abstract:
The disclosed two stage address decoder circuit (AD) for 1/64 decoder operation includes a first stage comprised of two predecoder circuits (PDP; PDQ) operable to develop predecoded output signals (P0, ..., P7; Q0, ..., Q7) in response to input address signals (A1, ..., A3; A4, ..., A6) and the corresponding inverted address signals. Each predecoder circuit consists of a low power high speed Differential Cascode Current Switch (DCCS) tree with its associated current source. The second or final decode stage (FD) is comprised of a plurality of final decoding circuits (FD1, ..., FD64). Each FD circuit consists of a 2 way OR gate dynamically activated through a switched current source. The inputs of the 2 way OR gate are connected to one couple of said predecoded output signals (P1, Q1; ...; P8, Q8). Final decoder circuits supplies a final decoded output signals (X1, ..., X64) to drive the word lines (WL1, ..., WL64) of a memory cell array (MA). The switched current source is triggered by a control signal (SWL) supplied by a clock generator (CG) so that the FD circuits consume power only when the control signal is active. The use of a DCCS tree in the predecoder and of a switched OR gate in the final decoder circuit gives the address decoder circuit a competitive speed-power product with a safe and glitchless behavior.
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Inventors:
SHIRUBEN RUFUORESUTEIE
DOMINIIKU OME
DOMINIIKU OME
Application Number:
JP24089989A
Publication Date:
October 02, 1996
Filing Date:
September 19, 1989
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G11C11/413; G11C8/10; G11C11/415; (IPC1-7): G11C11/413
Domestic Patent References:
| JP60254484A | ||||
| JP56112122A | ||||
| JP61242391A | ||||
| JP63220497A |
Attorney, Agent or Firm:
Jiro Yamamoto