Title:
【発明の名称】集積回路装置
Document Type and Number:
Japanese Patent JP2641968
Kind Code:
B2
Abstract:
PURPOSE:To detect malfunction of a load gate without enlarging an inner circuit by arranging, gates used as load gates in longitudinal rows in which NAND gates and NOR gates are placed alternately to construct a detection circuit for malfunction of the load gate. CONSTITUTION:Delay time Tpd1 from an input terminal A2 to an output terminal B1 is obtained by selecting a delay time measurement path P1 by means of a decoder and a selector, and delay time Tpd2 from an input terminal A2 to an output terminal B1 is obtained similarly by selecting a reference path P2 by means of a decoder and a selector, then, delay time per gate step can be obtained by calculation of (Tpd1-Tpd2)/number of gate steps. Furthermore, if the delay time measurement path P1 is selected by means of the decoder and the selector to check that output state of the output terminal B1 is always at '0' level in spite of the input level of the input terminal A2, malfunction of the load gate can be detected.
Inventors:
OKITA MUNEHISA
Application Number:
JP25087090A
Publication Date:
August 20, 1997
Filing Date:
September 20, 1990
Export Citation:
Assignee:
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
International Classes:
G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)