Title:
【発明の名称】ディジタル・フェーズ・ロック・ループおよびディジタル電圧制御発振器
Document Type and Number:
Japanese Patent JP2721115
Kind Code:
B2
Abstract:
A digital phase lock loop is provided, comprising a digital voltage controlled oscillator, a phase detector, and an up/down counter. The digital voltage controlled oscillator is responsive to a first set of control signals received from the up/down counter to provide an output signal. The phase detector receives and compares the frequency of the output signal with the frequency of a reference signal and, based on the comparison, outputs to the up/down counter a second control signal which determines the status of the first set of control signals. The digital voltage controlled oscillator comprises (i) an array of delay elements and (ii) a decoder for receiving the first set of the control signals from the up/down counter and for selectively activating one or more of the delay elements in response thereto. The decoder provides a separate output line for each of the delay elements which is to be selectively activated. The logic required to implement the decoder requires only a single AND gate and a single OR gate for each of the delay elements in the array.
Inventors:
JON EDOIN GERUSUBATSUHA
IRIA IOSHIFUOITSUCHI NOOFU
IRIA IOSHIFUOITSUCHI NOOFU
Application Number:
JP907094A
Publication Date:
March 04, 1998
Filing Date:
January 31, 1994
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
H03K3/03; H03K3/354; H03L7/06; H03L7/099; H03B5/20; H03B27/00; (IPC1-7): H03L7/06; H03K3/354; H03L7/099
Domestic Patent References:
| JP444413A | ||||
| JP5227020A | ||||
| JP4165809A | ||||
| JP5889031A | ||||
| JP5825710A | ||||
| JP5315899A | ||||
| JP5268002A |
Other References:
【文献】米国特許5132633(US,A)
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)