Title:
【発明の名称】半導体素子の製造方法
Document Type and Number:
Japanese Patent JP2847510
Kind Code:
B2
Abstract:
A fabrication method for a semiconductor memory device with a non-uniformly doped channel(hereinafter, called NUDC) formed in a semiconductor substrate with a thin central portion that becomes gradually thicker toward the edges of the substrate. The method includes forming an impurity-bearing layer on a semiconductor substrate, selectively etching the impurity containing layer in a manner such that the portion of the impurity-bearing layer serving as a gate region is formed to be thin at a central portion thereof and gradually thickens as it nears the edges thereof; forming a first conductive impurity region by driving the impurity from the impurity containing layer into the semiconductor substrate, stripping the impurity containing layer, sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a second conductive impurity region in the semiconductor substrate at the sides of the gate electrode.
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Inventors:
RII IEUN FUWAN
Application Number:
JP31788796A
Publication Date:
January 20, 1999
Filing Date:
November 28, 1996
Export Citation:
Assignee:
ERU JII SEMIKON CO LTD
International Classes:
H01L29/78; H01L21/225; H01L21/266; H01L21/336; H01L29/10; (IPC1-7): H01L29/78; H01L21/225
Attorney, Agent or Firm:
Fumio Sasashima (1 person outside)