Title:
【発明の名称】MOS型半導体装置
Document Type and Number:
Japanese Patent JP2941327
Kind Code:
B2
Abstract:
PURPOSE:To reduce a leakage current and to extend information holding time by setting the potential of a reverse conductivity type semiconductor substrate to the source.drain regions of a MOSFET to 0V, and bringing the gate voltage of the MOSFET at the time of holding information into coincidence with a flat band voltage in a MOS structure. CONSTITUTION:The potentials of a p-type substrate 1 and a p-type well layer 3 are set to 0V, the potential of an n-type shielding layer 2 is set to 1V, and the potential of a plate electrode 12 is set to 1.5V. The potentials of a bit line and a word line in a state for storing charge in a capacitor are respectively set to 3V and 5V. The potential of the word line in a state for holding charge stored in the capacitor is set to -0.8V. The potential of the bit line is set to 0-3V. In this case, since a gate electrode 7 is in a stored state and the potential of a storage node 10 is 3V, a depleted layer formed on the periphery of a junction made of an n-type layer 8 of a source region and a p-type well layer 2 is formed only of a lower part of the layer 8, parts of the n-type layer in contact with the element isolating regions 4, 5 and a part of the n-type layer in contact with a gate region, thereby reducing a leakage current.
Inventors:
OOYU SHIZUNORI
KAWAMOTO YOSHIFUMI
KAGA TOORU
KAWAMOTO YOSHIFUMI
KAGA TOORU
Application Number:
JP2196690A
Publication Date:
August 25, 1999
Filing Date:
February 02, 1990
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
International Classes:
H01L27/10; H01L21/8242; H01L27/108; H01L29/78; (IPC1-7): H01L27/108; H01L21/8242; H01L29/78
Domestic Patent References:
| JP6467967A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)