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Title:
【発明の名称】ブロックアクセスアプリケーションのための半導体メモリ装置
Document Type and Number:
Japanese Patent JP2998995
Kind Code:
B2
Abstract:
A semiconductor memory device is disclosed including a main memory configured as a dynamic random access memory array having rows and columns, combined with a secondary memory having a data register file, a transferring circuit for allowing transfer of data between the main memory and secondary memory, a first parallel-by-bit interface for random accesses to the main memory and a second parallel-by-bit interface for access to the seconday memory. Concurrent and independent accesses of the main and secondary memories is achieved while maintaining the integrity of data. Further included in the secondary memory is a data register file and a corresponding mask register file wherein the latter achieves selection of any combination of words in a row of the secondary memory for the purposes of transferring the same to the main memory.

Inventors:
Neemazy, Siamack
Application Number:
JP53123496A
Publication Date:
January 17, 2000
Filing Date:
April 11, 1996
Export Citation:
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Assignee:
Cirrus Logic, Incorporated
International Classes:
G11C11/401; G11C7/10; (IPC1-7): G11C11/401
Domestic Patent References:
JPS6238590A1987-02-19
JPH06267267A1994-09-22
JPH03286492A1991-12-17
Attorney, Agent or Firm:
Shusaku Yamamoto