Title:
【発明の名称】半導体装置の入力回路および出力回路ならびに半導体装置
Document Type and Number:
Japanese Patent JP3070510
Kind Code:
B2
Abstract:
In an input circuit of a semiconductor device, a CMOS inverter has first and second transistors connected in series between an external power supply and ground and complementarily operating in accordance with an input signal. The first and second transistors have a connection point connected to an output terminal. A first switching device is connected in parallel to the second transistor and turned on/off. A comparator compares a voltage from the external power supply with a predetermined reference voltage and outputs a reference signal representing a comparison result. A logic circuit performs a logical operation between the reference signal from the comparator and the input signal supplied to an input terminal of the CMOS inverter and ON/OFF-controls the first switching device on the basis of a logical operation result. The logic circuit turns off the first switching device when the reference signal from the comparator represents that the voltage from the external power supply is lower than the predetermined reference voltage, and otherwise, turns on/off the first switching device in accordance with a level of the input signal to the CMOS inverter.
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Inventors:
Yasuhiro Saruwatari
Application Number:
JP6796797A
Publication Date:
July 31, 2000
Filing Date:
March 21, 1997
Export Citation:
Assignee:
NEC
International Classes:
G11C11/407; G11C11/409; H03K19/00; H03K19/003; H03K19/0175; (IPC1-7): H03K19/003; H03K19/00; H03K19/0175
Domestic Patent References:
| JP7235869A | ||||
| JP6112802A | ||||
| JP884063A | ||||
| JP1216620A | ||||
| JP2153623A |
Attorney, Agent or Firm:
Masaki Yamakawa