Title:
【発明の名称】メモリー制御装置と液晶表示装置
Document Type and Number:
Japanese Patent JP3359270
Kind Code:
B2
Abstract:
A system can be realized by using a single frame memory, that is costly, to allow data write and data read operations continuously without suspending the video signal input. Such a memory controller comprises a serial/parallel converter section for converting serial input data into parallel data, an FIFO memory section for temporarily storing converted data, a memory section connected to the FIFO memory section to store data for a frame and a second FIFO memory section for temporarily storing the data read out from the frame memory section. The data bit width of said memory section is made equal to n times of the bit width of said input data so that data for a number of frames up to as many as (n-2) times of the number of input pixels can be read out of said memory section for said input data while the frequency of accessing said memory section can be reduced to a half or less than a half of the video signal input frequency.
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Inventors:
Yoshihiro Terashima
Yukihiko Sakashita
Yukihiko Sakashita
Application Number:
JP29290597A
Publication Date:
December 24, 2002
Filing Date:
October 24, 1997
Export Citation:
Assignee:
Canon Inc
International Classes:
G02F1/133; G09G3/36; G09G5/00; G09G5/18; G09G5/39; (IPC1-7): G09G3/36; G02F1/133; G09G5/00; G09G5/18
Domestic Patent References:
| JP961785A | ||||
| JP564114A | ||||
| JP622284A | ||||
| JP662685U |
Attorney, Agent or Firm:
Johei Yamashita