Title:
半導体集積回路装置ならびにD/A変換装置およびA/D変換装置
Document Type and Number:
Japanese Patent JP3549499
Kind Code:
B2
Abstract:
A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.
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Inventors:
Mimi Miyata
Kenji Murata
Kenji Murata
Application Number:
JP2001203216A
Publication Date:
August 04, 2004
Filing Date:
July 04, 2001
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L27/04; H01L21/822; H01L23/522; H01L27/08; (IPC1-7): H01L21/822; H01L27/04
Domestic Patent References:
| JP2140958A | ||||
| JP5047943A | ||||
| JP3285333A | ||||
| JP1248641A | ||||
| JP10303373A | ||||
| JP5235266A |
Attorney, Agent or Firm:
Hiroshi Maeda