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Patent Searching and Data


Title:
BOOSTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6240060
Kind Code:
A
Abstract:

PURPOSE: To obtain the voltage of power supply voltage or more by the small number of elements by using an E/D type inverter in which the load side is formed in a depletion type transistor and the drive side in an enhancement type transistor.

CONSTITUTION: Two pairs of E/D inverters in which load-side depletion type transistors Q2, Q5 and drive side enhancement type transistors Q3, Q6 ar combined are connected so that the two load-side transistors Q2 and Q5 are driven by an output N2 from the first inverter. A diode element Q1 is connected between the first load-side transistor Q2 and a power supply Vcc. A node N1 for the first inverter and an output N3 from the second inverter are connected by a capacitance Q4 for boosting trap, both drive-side transistors Q3 and Q6 are controlled by a common input IN, and boosting voltage is acquired from the output N2 from the first inverter.


Inventors:
NAKANO MASAO
Application Number:
JP17738785A
Publication Date:
February 21, 1987
Filing Date:
August 12, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L27/04; H01L21/822; H02M3/07; (IPC1-7): H01L27/04; H02M3/07
Attorney, Agent or Firm:
Fumihiro Hasegawa