Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP3573589
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To increase the gate width of a bank cell as much as possible, without increasing the area of the bank region by connecting a conductive layer to an impurity-diffused layer through openings of gate electrodes existing on this diffused layer. SOLUTION: Bank regions BANK0-2 corresponding to blocks are provided on a predetermined surface region of a first-conductivity-type (p-type) semiconductor substrate. The region BANK1 comprises a plurality of width bit lines SB1A-SB7A of a second-conductivity-type diffused layer on the substrate, a plurality of polysilicon word lines WL1A-WL32A crossing the width bit lines and memory cells disposed between the adjacent width bit lines; the cells using the word lines as gate electrodes. Auxiliary conductive regions BB11, 12, BB21, 22 are connected to main bit lines and main ground lines of metal wrings through contact holes C11, 12, C21, 22 formed at each opening, thereby increasing the bit line current.
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Inventors:
Satoshi Aoki
Yasuhiro Sasaki
Yasuhiro Sasaki
Application Number:
JP4118797A
Publication Date:
October 06, 2004
Filing Date:
February 25, 1997
Export Citation:
Assignee:
Sharp Corporation
International Classes:
H01L29/78; H01L21/8242; H01L21/8246; H01L27/108; H01L27/112; (IPC1-7): H01L21/8246; H01L21/8242; H01L27/108; H01L27/112; H01L29/78
Domestic Patent References:
| JP2119177A | ||||
| JP5152536A | ||||
| JP6097395A | ||||
| JP6104406A | ||||
| JP6120451A | ||||
| JP6350057A | ||||
| JP7135261A | ||||
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| JP8330448A | ||||
| JP9181161A | ||||
| JP9312350A | ||||
| JP10223780A | ||||
| JP10223781A |
Attorney, Agent or Firm:
Shintaro Nogawa