Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP3626510
Kind Code:
B2
Abstract:
PURPOSE:To allow accurate read out of data from a memory cell even if the layout area of a DRAM is decreased or the memory capacity thereof is increased. CONSTITUTION:A plurality of pairs of sub-bit line BLs and /BLs are arranged for a pair of relatively long main bit lines BLm and /BLm. The sub-bit line BLs or /BLs is connected with the main bit line BLm or /BLm through a transfer gate T or /T. The parasitic capacitance of the pair of main bit lines BLm and /BLm per unit length is set one fourth or less that of the pair of sub-bit line.
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Inventors:
Mikio Asakura
Masaki Tsukide
Kazuyasu Fujishima
Masaki Tsukide
Kazuyasu Fujishima
Application Number:
JP7332994A
Publication Date:
March 09, 2005
Filing Date:
April 12, 1994
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C11/401; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/401
Domestic Patent References:
| JP2148496A | ||||
| JP2161700A | ||||
| JP4053083A | ||||
| JP61110400A | ||||
| JP60234296A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai