Title:
システム校正付き電荷再分布アナログ-デジタル変換器
Document Type and Number:
Japanese Patent JP3748886
Kind Code:
B2
Abstract:
A charge redistribution analog-to-digital converter. This converter includes an offset correcting circuit operatively connected in parallel with a capacitor array and responsive to a sampling input of the analog-to-digital converter, and a gain correcting circuit operatively connected in parallel with a sampling capacitor and responsive to the sampling input of the analog-to-digital converter. In another general aspect, an analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, that includes adjusting an input offset of an input of the analog-to-digital converter and adjusting a gain offset of the analog-to-digital converter. The steps of adjusting are then repeated until a predetermined level of error is achieved for the analog-to-digital converter.
Inventors:
Cotter, martin gee
Garavan, Patrick Jay
Garavan, Patrick Jay
Application Number:
JP52847495A
Publication Date:
February 22, 2006
Filing Date:
April 27, 1995
Export Citation:
Assignee:
Analog Devices, Inc.
International Classes:
H03M1/38; H03M1/10; H03M1/46; H03M1/80
Foreign References:
| US4654815 | ||||
| EP0064147A2 | ||||
| EP0360914A1 |
Attorney, Agent or Firm:
Kazuo Shamoto
Shosuke Imai
Tadashi Masui
Tadahiko Kurita
Yasushi Kobayashi
Yoshio Akimoto
Shosuke Imai
Tadashi Masui
Tadahiko Kurita
Yasushi Kobayashi
Yoshio Akimoto