Title:
電力増幅システムおよび移動体通信端末装置
Document Type and Number:
Japanese Patent JP3890193
Kind Code:
B2
Abstract:
A power amplifier system has a high frequency power amplifier circuit section employing source-grounded enhancement type n-channel MESFETs for receiving a drain bias voltage and a gate bias voltage of zero volts or positive low potentials supplied from a unipolar power supply, and amplifying a superposed input signal therewith to output an amplified signal indicative of a change in drain currents. An output matching circuit section applies impedance matching to the amplified signal and outputs the resultant signal. A gate bias voltage circuit section supplies a gate bias voltage to the high frequency power amplifier circuit. When a forward direct current gate voltage is applied to a gate terminal with a source terminal coupled to ground, the DC gate voltage becomes greater than or equal to 0.65 volts, the DC gate voltage causing a gate current value per gate width of 100 micrometers to exceed 100 microamperes.
Inventors:
Atsushi Kurokawa
Masao Yamane
Masao Yamane
Application Number:
JP2000525972A
Publication Date:
March 07, 2007
Filing Date:
December 22, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H03F3/24; H03F1/30; H03F1/56; H03F3/193; H04B1/04
Domestic Patent References:
| JP5995709A | ||||
| JP8222937A | ||||
| JP98061A | ||||
| JP1188065A |
Attorney, Agent or Firm:
Yamato Tsutsui
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