Title:
半導体装置、メモリシステムおよび電子機器
Document Type and Number:
Japanese Patent JP4006565
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a high-speed SRAM and whose power consumption can be lowered. SOLUTION: The memory cell of the SRAM has a structure, in which five conductive layers are provided in the upper part of a field. Subword lines 23a, 23b in the first-layer conductive layer are situated, so as to be separated from an active region 13 as the field viewed from a plane. The active region 13 does not extend to the lower part of the subword lines 23a, 23b. Since the overlapping part of the active region 13 with the subword line 23a (or 23b) is not generated, stray capacitance caused by the overlap part can be eliminated.
Inventors:
Karasawa Junichi
Application Number:
JP2001031242A
Publication Date:
November 14, 2007
Filing Date:
February 07, 2001
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L21/8244; H01L27/10; H01L27/11
Domestic Patent References:
| JP2000031298A | ||||
| JP2000036543A |
Attorney, Agent or Firm:
Yukio Fuse
Mitsue Obuchi
Mitsue Obuchi