Title:
半導体装置、メモリシステムおよび電子機器
Document Type and Number:
Japanese Patent JP4006566
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an SRAM which can increase the stability of a memory cell. SOLUTION: The memory cell of the SRAM has a structure, in which five conductive layers are provided in the upper part of a field. A flip-flop is constituted of the first-layer to third-layer conductive layers from among them. A gate width WD of drive transistors Q3, Q4, expressed by the width W11a of a drive transistor formation region 11a, is larger than a gate width WT of transfer transistors Q1, Q2 expressed by a width W11b of a transfer transistor formation region 11b. A gate length LT of the transfer transistors Q1, Q2, expressed by widths W23a, W23b of subword lines 23a, 23b, is larger than a gate length LD of the drive transistors Q3, Q4 expressed by widths W21a, W21b of gate-to-gate electrode layers 21a, 21b. Thereby, a beta ratio can be increased.
Inventors:
Karasawa Junichi
Application Number:
JP2001031243A
Publication Date:
November 14, 2007
Filing Date:
February 07, 2001
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L21/768; H01L21/8244; H01L27/11
Domestic Patent References:
| JP2000031298A | ||||
| JP2000036543A | ||||
| JP10125803A | ||||
| JP2002064154A |
Attorney, Agent or Firm:
Yukio Fuse
Mitsue Obuchi
Mitsue Obuchi