Title:
半導体デバイス中に線間容量の低減化された相互接続線を作製する方法
Document Type and Number:
Japanese Patent JP4014234
Kind Code:
B2
Abstract:
An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on. One advantage of the invention is providing a metallization scheme that reduces line-to-line capacitance. A further advantage of the invention is providing a metallization scheme that reduces crosstalk and power dissipation. A further advantage of the invention is providing a dielectric layer between interconnect lines having a lower density and a lower dielectric constant than dense silicon dioxide.
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Inventors:
Thin-Posing
Application Number:
JP16676295A
Publication Date:
November 28, 2007
Filing Date:
May 29, 1995
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
H01L21/768; H01L21/312; H01L21/316; H01L23/522; H01L23/532; H01L21/314
Domestic Patent References:
| JP4311059A | ||||
| JP63208248A | ||||
| JP4125929A | ||||
| JP7240460A |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo