Title:
表示制御装置および携帯用電子機器
Document Type and Number:
Japanese Patent JP4132654
Kind Code:
B2
Abstract:
The display RAM built into a conventional display control device uses a system in which data are sequentially written word by word, it involves a problem that, if th write speed is to be raised to match the transfer speed of display data from the microprocessor, the power consumption will increase in proportion to the transfer speed. The width (number of bits) of write data to a display RAM in a display control device is set to be an integral multiple of the width of write data supplied from an external microprocessor or the like, and two stages of latch circuits for holding write data equivalent to one row of the display RAM are provided. A few cycles' equivalent of the write data supplied from the microprocessor or the like is taken into the first stage of latch circuits and, when the data are ready, they are collectively transferred to the second stage of latch circuits, so that the data held by the second stage of latch circuits can be collectively transferred by a transfer gate to the display RAM for displaying.
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Inventors:
Kunihiko Tani
Yoshikazu Yokota
Goro Sakamaki
Oyama
Yoshikazu Yokota
Goro Sakamaki
Oyama
Application Number:
JP2000383012A
Publication Date:
August 13, 2008
Filing Date:
December 18, 2000
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G02F1/133; G09G5/00; G09G3/20; G09G3/36; G09G5/393
Domestic Patent References:
| JP2006053574A | ||||
| JP10282938A | ||||
| JP10177790A | ||||
| JP9320259A | ||||
| JP10105120A | ||||
| JP2000260181A | ||||
| JP8139290A | ||||
| JP10092177A |
Attorney, Agent or Firm:
Shizuyo Tamamura