Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4299848
Kind Code:
B2
Abstract:
A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit block and the row of sense amplifiers attached to the unit block; and control means for controlling the switch means so as to form a transfer path from the row of sense amplifiers attached to a predetermined the unit block leading to the row of sense amplifiers as a saving destination not attached to the predetermined the unit block. This row of sense amplifiers attached to the predetermined the unit block functions as a cache memory.
Inventors:
Kazuhiko Kajitani
Application Number:
JP2006217575A
Publication Date:
July 22, 2009
Filing Date:
August 09, 2006
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
G11C11/401; G11C11/406
Domestic Patent References:
| JP8129877A | ||||
| JP5182452A | ||||
| JP5159566A | ||||
| JP5159567A | ||||
| JP2004103657A | ||||
| JP64084495A | ||||
| JP6314240A | ||||
| JP2003067247A |
Attorney, Agent or Firm:
Kohei Shuto