Title:
半導体記憶装置及びそのリフレッシュ制御方法
Document Type and Number:
Japanese Patent JP4299849
Kind Code:
B2
Abstract:
A semiconductor memory device has a refresh control circuit for switchingly controlling a first refresh mode in which access to the memory cell array from outside is prohibited while retaining data and a second refresh mode in which access to the memory cell array from outside is permitted while retaining data and for performing the refresh operation of the memory cells corresponding to a selected word line, and a designating circuit for individually designating a portion to be refreshed in the first refresh mode and a portion to be refreshed in the second refresh mode. In the semiconductor memory device, the refresh control circuit performs the refresh operation when the portion to which the selected word line belongs is designated to be refreshed, and does not perform the refresh operation when the portion to which the selected word line belongs is not designated to be refreshed.
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Inventors:
Kazuhiko Kajitani
Application Number:
JP2006225851A
Publication Date:
July 22, 2009
Filing Date:
August 22, 2006
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
G11C11/406; G11C11/403
Domestic Patent References:
| JP2002373489A | ||||
| JP2000298982A | ||||
| JP2001093278A | ||||
| JP2006147123A | ||||
| JP2192096A | ||||
| JP2002334576A |
Attorney, Agent or Firm:
Kohei Shuto