Title:
半導体装置
Document Type and Number:
Japanese Patent JP4301760
Kind Code:
B2
Abstract:
A threshold compensating circuit generates a bias potential VBIAS, that is, a threshold voltage of a MOS transistor offset by a given value. A gate-source voltage having compensation for variation in threshold voltage is thus applied to a transistor. By using a differential amplifier having this transistor as a current source, a voltage down-converter less susceptible to variation in threshold voltage caused by process variation and temperature can be implemented.
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Inventors:
Hiroaki Nakai
Application Number:
JP2002049685A
Publication Date:
July 22, 2009
Filing Date:
February 26, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C11/413; H01L21/8238; G05F1/46; G05F1/56; G11C11/407; G11C11/4074; H01L21/822; H01L27/04; H01L27/092; H01L27/10
Domestic Patent References:
| JP7044255A | ||||
| JP2000353394A | ||||
| JP2001028523A | ||||
| JP2001067048A | ||||
| JP11150429A | ||||
| JP10322142A | ||||
| JP10112614A | ||||
| JP9186294A | ||||
| JP5183356A | ||||
| JP8288754A | ||||
| JP10302464A | ||||
| JP2000174568A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai