Title:
カットベース手法を用いたリタイミング回路
Document Type and Number:
Japanese Patent JP4473264
Kind Code:
B2
Abstract:
Methods and apparatus for retiming an integrated circuit are described. According to certain embodiments, the retiming comprises performing a timing analysis for one or more paths in the integrated circuit to obtain slack values, selecting one of the paths based on the slack values obtained, and determining a retimeable cut along the path selected. The retimeable cut in these exemplary embodiments comprises a set of input pins for one or more logic instances in the integrated circuit to which one or more retimed sequential elements can be coupled in order to improve the slack value of the path selected. In particular embodiments, the retimeable cut is automatically selected from multiple possible cuts along the path selected. Other embodiments for retiming integrated circuits are disclosed, as well as integrated circuits and circuit design databases retimed by the disclosed methods. Computer-executable media storing instructions for performing the disclosed methods are also disclosed.
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Inventors:
Suary, Peter
Wang, Dong Shen
Wang, Dong Shen
Application Number:
JP2006507445A
Publication Date:
June 02, 2010
Filing Date:
March 18, 2004
Export Citation:
Assignee:
Mentor Graphics Corporation
International Classes:
G06F17/50; G06F9/45; G06F9/455; H01L
Domestic Patent References:
| JP6290232A | ||||
| JP7334531A |
Other References:
Singh D P, et al,Integrated Retiming and Plecement for Field Programmable Gate Arrays,2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays,米国,ACM,2002年 2月24日,pages 67-76
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Katsuhiko Sumiyoshi
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Katsuhiko Sumiyoshi