メモリワードアレイ構成およびメモリアクセス予測結合

Japanese Patent JP4496209

B2

Described systems and methods allow a reduction in the memory bandwidth required in video coding (decoding/encoding) applications. According to a first aspect, the data assigned to each memory word is chosen to correspond to a 2D subarray of a larger array such as a macroblock. An array memory word organization allows reducing both the average and worst-case bandwidth required to retrieve predictions from memory in video coding applications, particularly for memory word sizes (memory bus widths) larger than the size of typical predictions. According to a second aspect, two or more 2D subarrays such as video predictions are retrieved from memory simultaneously as part of a larger 2D array, if retrieving the larger array requires fewer clock cycles than retrieving the subarrays individually. Allowing the combination of multiple predictions in one memory access operation can lead to a reduction in the average bandwidth required to retrieve predictions from memory.

JPH08336140	MOTION VECTOR ESTIMATING METHOD
JPH1093971	MOVING VECTOR DETECTION DEVICE

Sithmus, Sorinsea.

JP2006501222A

July 07, 2010

March 03, 2004

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Morbilligen Corporation

H04N7/32; G06F12/02; H04N7/12; H04N7/26; H03M

JP8195960A

US6335950

Kim, Hansoo and Park, In-Cheol,Array Address Translation for SDRAM-Based Video Processing Applications,Proc. of SPIE Visual Communications and Image Processing 2000,2000年,Vol.4067
Zhou,M.,Lainema,J., and Karczewicz,M.,More Results on Restriction on Vector Spread-out in 8x8 Partitioning Mode,Joint Video Team (JVT) of ISO/IEC MPEG & ITU-T VCEG(ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6) JVT-E041,2002年10月 9日,URL,http://wftp3.itu.int/av-arch/jvt-site/2002_10_Geneva/JVT-E041.doc

Inaoka cultivation
Mio Kawasaki

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