Title:
絶縁ゲート型バイポーラトランジスタ
Document Type and Number:
Japanese Patent JP4566470
Kind Code:
B2
Abstract:
NOVELTY - The transistor has several n+ impurity areas (11) selectively formed on the surface (103) covering the collector electrode (10). The n+ impurity areas which are not in connection with the n-type conductive layer (80), are formed in accordance with the respective channel areas (CH1a-CH1d).
USE - Insulation gate type bipolar transistor for inverter.
ADVANTAGE - Since the n+ impurity areas are formed in accordance with respective channel areas the leakage current is effectively reduced, hence reliability is enhanced.
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Inventors:
Eisuke Suekawa
Application Number:
JP2001216135A
Publication Date:
October 20, 2010
Filing Date:
July 17, 2001
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L29/739; H01L29/08; H01L29/78
Domestic Patent References:
| JP2000004017A | ||||
| JP5090593A | ||||
| JP4072669A | ||||
| JP3204976A | ||||
| JP5152574A | ||||
| JP1080077A | ||||
| JP11054519A |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita