Title:
半導体装置
Document Type and Number:
Japanese Patent JP4583725
Kind Code:
B2
Abstract:
A terminating resistance element of an LSI chip has an N- type impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an N+ type impurity diffusion layer formed at the surface of the N- type impurity diffusion region, and a pair of electrodes formed at respective ends at the surface of the N+ type impurity diffusion layer. The N- type impurity diffusion region has an impurity concentration lower than the impurity concentration of the N+ type impurity diffusion layer. Therefore, the capacitance of the PN junction becomes smaller as compared to the conventional case where the N type impurity diffusion layer is provided directly at the surface of a P type semiconductor substrate. Therefore, reflection and attenuation of an input signal are suppressed.
Inventors:
Yasushi Hayakawa
Katsushi Asahina
Katsushi Asahina
Application Number:
JP2003138900A
Publication Date:
November 17, 2010
Filing Date:
May 16, 2003
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/822; H01L27/04; H01L21/331; H01L21/8234; H01L21/8238; H01L27/06; H01L27/08; H01L27/092; H01L29/8605; H01L31/0328
Domestic Patent References:
| JP8139272A | ||||
| JP6045601A | ||||
| JP55091153A | ||||
| JP2002076270A | ||||
| JP2003068082A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Masayuki Sakai
Nobuo Arakawa
Masato Sasaki
Hisato Noda
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Masayuki Sakai
Nobuo Arakawa
Masato Sasaki
Hisato Noda