To drastically reduce violation in timing analysis after a layout design to drastically reduce a period of layout correction in a logic circuit and a rework of a logic design stage.

A logic connection information extraction part 3 extracts logic connection information from a logic circuit diagram stored in a logic circuit diagram storage part 2, and a layout editing part 5 performs the layout design according to the logic connection information. At that time, an RC extraction part 7 extracts parasitic capacity or parasitic resistance of laid out wiring, and a comparison part 9 compares it with a parasitic resistance value or a parasitic capacity value extracted by the logic connection information extraction part 3. When an RC value/violation information generation part 10 decides that the parasitic capacity or the parasitic resistance extracted by the RC extraction part 7 is larger than the parasitic resistance value or the parasitic capacity value extracted by the logic connection information extraction part 3, the RC value/violation information generation part 10 generates error information, and displays the error information on a layout diagram of a display part 11 through the layout editing part 5 to design the layout in conformity to restriction added in the logic design stage.

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