Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP5126060
Kind Code:
B2
Abstract:
There is provided a semiconductor device having excellent device characteristics and reliability in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be values necessary for a low-power device. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI substrate. The pMOS transistor is a fully depleted MOS transistor including a first gate electrode comprising at least one type of crystalline phase selected from the group consisting of a WSi2 crystalline phase, an MoSi2 crystalline phase, an NiSi crystalline phase, and an NiSi2 crystalline phase as silicide region (1). The nMOS transistor is a fully depleted MOS transistor comprising at least one type of crystalline phase selected from the group consisting of a PtSi crystalline phase, a Pt2Si crystalline phase, an IrSi crystalline phase, an Ni2Si crystalline phase, and an Ni3Si crystalline phase as silicide region (2).
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Inventors:
Kensuke Takahashi
Application Number:
JP2008526749A
Publication Date:
January 23, 2013
Filing Date:
July 23, 2007
Export Citation:
Assignee:
NEC
International Classes:
H01L29/786; H01L21/28; H01L21/283; H01L21/8238; H01L27/08; H01L27/092; H01L29/423; H01L29/49
Domestic Patent References:
| JP2004356472A | 2004-12-16 | |||
| JP2006156807A | 2006-06-15 | |||
| JP2005085949A | 2005-03-31 | |||
| JP2003258121A | 2003-09-12 | |||
| JP2003123625A | 2003-04-25 |
Foreign References:
| WO2006001271A1 | 2006-01-05 |
Attorney, Agent or Firm:
Akio Miyazaki
Ishibashi Masayuki
Masaaki Ogata
Ishibashi Masayuki
Masaaki Ogata