Title:
半導体回路に一連の半導体メモリの浮動ゲートメモリセルを形成する自己調整方法
Document Type and Number:
Japanese Patent JP5140219
Kind Code:
B2
Abstract:
A self aligned method forms a semiconductor memory array of floating gate memory cells in a semiconductor substrate which has a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction. Floating gates (14) are formed in each of the active regions by forming a conductive layer of material. Trenches are formed in the row direction across the active regions, and are filled with a conductive material to form blocks (46) of conductive material for the control gates. Sidewall spacers (44) of conductive material are formed along the floating gate blocks (46) to give the floating gates protruding portions that extend over the floating gate (14).
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Inventors:
Chi Shin Wan
Application Number:
JP2001284960A
Publication Date:
February 06, 2013
Filing Date:
September 19, 2001
Export Citation:
Assignee:
SILICON STORAGE TECHNOLOGY INCORPORATED
International Classes:
H01L21/336; G11C11/34; H01L21/28; H01L21/8238; H01L21/8247; H01L27/115; H01L29/423; H01L29/788; H01L29/792
Domestic Patent References:
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| JP6506798A | ||||
| JP9064208A | ||||
| JP8213486A | ||||
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Foreign References:
| US5572054 | ||||
| US5841162 |
Attorney, Agent or Firm:
Yuzo Yamazaki
Toshiaki Akamatsu
Ono Wataru
Okuko Masako
Tadao Naito
Chihiro Imai
Takeko Miko
Kei Kiuchi
Hiroaki Nishimura
Toshiaki Akamatsu
Ono Wataru
Okuko Masako
Tadao Naito
Chihiro Imai
Takeko Miko
Kei Kiuchi
Hiroaki Nishimura