Title:
半導体ウェハの製造方法
Document Type and Number:
Japanese Patent JP5481284
Kind Code:
B2
Abstract:
Semiconductor wafers are produced by a process of: a) providing a semiconductor wafer by cutting a silicon ingot into wafers; b) rounding the edge of the wafer, so that the wafer comprises plane surfaces on the frontside and backside and rounded oblique surfaces in the edge region; c) polishing the frontside and backside of the wafer, the frontside being polished by chemical-mechanical polishing using a polishing pad which is free of abrasive fixed in the polishing pad; backside polishing being carried out in three steps, using a polishing pad containing fixed abrasive which is pressed onto the backside of the wafer, a polishing agent free of solids introduced between the polishing pad and the backside of the wafer in the first step, a polishing agent containing abrasive being introduced in the second and third steps, a polishing pressure of 8-15 psi in the first and second steps being reduced to 0.5-5 psi in the third step.
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Inventors:
Jürgen Schwandner
Application Number:
JP2010142493A
Publication Date:
April 23, 2014
Filing Date:
June 23, 2010
Export Citation:
Assignee:
Siltronic AG
International Classes:
H01L21/304; B24B37/00; B24B37/04; H01L21/205
Domestic Patent References:
| JP2009033159A | ||||
| JP2002231669A | ||||
| JP2004096112A | ||||
| JP9038849A | ||||
| JP2003249466A | ||||
| JP2004356336A | ||||
| JP2002160155A | ||||
| JP2002512894A | ||||
| JP2000315665A | ||||
| JP2001135605A |
Attorney, Agent or Firm:
Fukami patent office