Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5562874
Kind Code:
B2
Abstract:
The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.
More Like This:
| JP5288476 | Substrate manufacturing methods, circuit boards, and electronic devices |
| JP2002050718 | SEMICONDUCTOR DEVICE |
| JPS61150225 | MANUFACTURE OF SEMICONDUCTOR DEVICE |
Inventors:
Okada Makio
Kuratani Hidetoshi
Toshio Tanabe
Fujisaki Yoshinori
Kotaro Arita
Kuratani Hidetoshi
Toshio Tanabe
Fujisaki Yoshinori
Kotaro Arita
Application Number:
JP2011003560A
Publication Date:
July 30, 2014
Filing Date:
January 12, 2011
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/56; B29C45/00; B29C45/02; B29C45/26
Domestic Patent References:
| JP7254664A | ||||
| JP10270602A | ||||
| JP2002076038A |
Attorney, Agent or Firm:
Yamato Tsutsui
Atsushi Sugada
Akiko Tsutsui
Toru Nakahara
Tetsuya Sakaji
Atsushi Sugada
Akiko Tsutsui
Toru Nakahara
Tetsuya Sakaji