Title:
歪補償装置、送信機および歪補償方法
Document Type and Number:
Japanese Patent JP5751056
Kind Code:
B2
Abstract:
A distortion compensation apparatus includes an amplifying unit, a plurality of distortion compensation coefficient storage units, a first address generating unit, a second address generating unit, and a distortion compensating unit. The amplifying unit amplifies an input signal. A plurality of distortion compensation coefficient storage units store the distortion compensation coefficients for compensating for the distortion of the amplifying unit by being associated with two different addresses. The first address generating unit generates a first address based on the current input signal. The second address generating unit generates a second address different from the first address based on the previous input signal. The distortion compensating unit obtains the distortion compensation coefficient corresponding to a combination of the first and second addresses from each of the distortion compensation coefficient storage units and performs a pre-distortion processing for the current input signal to the amplifying unit using the obtained distortion compensation coefficient.
Inventors:
Hiroyoshi Ishikawa
Fudaba Shinwa
Kazuo Hase
Fudaba Shinwa
Kazuo Hase
Application Number:
JP2011155970A
Publication Date:
July 22, 2015
Filing Date:
July 14, 2011
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03F1/32; H03F3/24; H04B1/04
Domestic Patent References:
| JP2011010107A | ||||
| JP2010074723A | ||||
| JP2012238966A |
Foreign References:
| US20100093290 |
Attorney, Agent or Firm:
Hiroaki Sakai