キャッシュメモリの利用トレンドに基づく複数セットグループ内のウェイごとの動的パワー供給 - Via Alliance Semiconductor Company Limited

Title:

キャッシュメモリの利用トレンドに基づく複数セットグループ内のウェイごとの動的パワー供給

Document Type and Number:

Japanese Patent JP6267314

Kind Code:

B2

Abstract:

A set associative cache memory comprises an M x N memory array of storage entries arranged as M sets by N ways, both M and N are integers greater than one. Within each group of P mutually exclusive groups of the M sets, the N ways are separately powerable. A controller, for each group of the P groups, monitors a utilization trend of the group and dynamically causes power to be provided to a different number of ways of the N ways of the group during different time instances based on the utilization trend.

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Inventors:

Douglas Earl Reed
Rodney E Hooker

Application Number:

JP2016250866A

Publication Date:

January 24, 2018

Filing Date:

December 26, 2016

Export Citation:

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Assignee:

Via Alliance Semiconductor Company Limited

International Classes:

G06F12/08

Domestic Patent References:

JP950401A
JP2006190341A

Foreign References:

US20150309939
US20140297959
US20140122824

Attorney, Agent or Firm:

Tadashige Ito
Tadahiko Ito
Shinsuke Onuki

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