方法、メモリサブシステム、電子デバイス、コンピュータプログラム、装置およびコンピュータ可読記録媒体

Title:

方法、メモリサブシステム、電子デバイス、コンピュータプログラム、装置およびコンピュータ可読記録媒体

Document Type and Number:

Japanese Patent JP6372899

Kind Code:

B2

Abstract:

The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or infinite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

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Inventors:

Rajwade, Shantanu
Karavade, Planaph
Mirke, Neil
Palat, Krishna
Rough Nazan, Shayam Sunder

Application Number:

JP2016551275A

Publication Date:

August 15, 2018

Filing Date:

March 27, 2015

Export Citation:

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Assignee:

INTEL CORPORATION

International Classes:

G11C16/34; G11C16/04

Domestic Patent References:

JP2012234600A

Foreign References:

US20110157995
US20120300550
US20140036595

Attorney, Agent or Firm:

Longhua International Patent Service Corporation

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