Title:
セグメント化された演算を実行するためのデータ処理装置及び方法
Document Type and Number:
Japanese Patent JP6469120
Kind Code:
B2
Abstract:
A data processing apparatus and method are provided for performing segmented operations. The data processing apparatus comprises a vector register store for storing vector operands, and vector processing circuitry providing N lanes of parallel processing, and arranged to perform a segmented operation on up to N data elements provided by a specified vector operand, each data element being allocated to one of the N lanes. The up to N data elements forms a plurality of segments, and performance of the segmented operation comprises performing a separate operation on the data elements of each segment, the separate operation involving interaction between the lanes containing the data elements of the associated segment. Predicate generation circuitry is responsive to a compute descriptor instruction specifying an input vector operand comprising a plurality of segment descriptors, to generate per lane predicate information used by the vector processing circuitry when performing the segmented operation to maintain a boundary between each of the plurality of segments. As a result, interaction between lanes containing data elements from different segments is prevented. This allows very effective utilisation of the lanes of parallel processing within the vector processing circuitry to be achieved.
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Inventors:
Ayeol-Monono, Mbow
Reed, alastair david
Betcher, matias rotor
Gabrielli, Giacomo
Reed, alastair david
Betcher, matias rotor
Gabrielli, Giacomo
Application Number:
JP2016549398A
Publication Date:
February 13, 2019
Filing Date:
January 21, 2015
Export Citation:
Assignee:
RM Limited
International Classes:
G06F15/80; G06F17/16
Foreign References:
| US20120210081 | ||||
| US20130124823 |
Attorney, Agent or Firm:
Asamura patent office