Title:
クロックデータリカバリ回路、位相同期回路及び半導体装置
Document Type and Number:
Japanese Patent JP6479449
Kind Code:
B2
Abstract:
A clock data recovery circuit is configured to receive an input data signal formed of a series of input data pieces synchronized with a reference clock signal, and to generate a regenerated clock signal. The clock data recovery circuit includes a regenerated clock generating circuit; a latch circuit; a comparison circuit; a logical sum signal generating circuit; and a charge pump.
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Inventors:
Harayama Kunihiro
Application Number:
JP2014251484A
Publication Date:
March 06, 2019
Filing Date:
December 12, 2014
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
H03L7/08; H03L7/089
Domestic Patent References:
| JP2012120100A | ||||
| JP7038432A | ||||
| JP2011120106A |
Foreign References:
| US20070001713 | ||||
| US6249159 |
Attorney, Agent or Firm:
Motohiko Fujimura
Shinji Takano
Shinji Takano