Title:
半導体装置
Document Type and Number:
Japanese Patent JP6611782
Kind Code:
B2
Abstract:
When a columnar spacer is provided in a region overlapping with a TFT, there is a concern that pressure will be applied when attaching a pair of substrates to each other, which may result in the TFT being adversely affected and a crack forming. A dummy layer is formed of an inorganic material below a columnar spacer which is formed in a position overlapping with the TFT. The dummy layer is located in the position overlapping with the TFT, so that pressure applied to the TFT in a step of attaching the pair of substrates is distributed and relieved. The dummy layer is preferably formed of the same material as a pixel electrode so that it is formed without an increase in the number of processing steps.
Inventors:
Fujikawa Saito
Kunio Hosoya
Kunio Hosoya
Application Number:
JP2017233578A
Publication Date:
November 27, 2019
Filing Date:
December 05, 2017
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G02F1/1339; G02F1/1368; H05B44/00
Domestic Patent References:
| JP10068955A | ||||
| JP2000131714A | ||||
| JP11119252A | ||||
| JP2001036019A |
Foreign References:
| KR1020050035382A |