Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP6620388
Kind Code:
B2
Abstract:
A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.
Inventors:
Koji Arai
Application Number:
JP2017224452A
Publication Date:
December 18, 2019
Filing Date:
November 22, 2017
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/8244; H01L27/11; G11C5/00; G11C11/412; G11C11/417
Domestic Patent References:
| JP10178110A | ||||
| JP7130877A | ||||
| JP7122655A | ||||
| JP7007089A | ||||
| JP2000232168A |
Foreign References:
| US5126279 |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita