Title:
半導体装置
Document Type and Number:
Japanese Patent JP6645793
Kind Code:
B2
Abstract:
A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing generation circuit. The latch circuit has a function of receiving a pulse signal and a reset signal and outputting a first signal. The delay circuit has a function of receiving the first signal and outputting a second signal. The first signal controls power supply to the arithmetic circuit and the delay circuit. The second signal is obtained by delaying the first signal so as to correspond to a delay in a critical path of the arithmetic circuit. The first output timing generation circuit has a function of receiving a third signal obtained by a logical operation on the first signal and the second signal and outputting the reset signal.
Inventors:
Yoshimoto Kurokawa
Application Number:
JP2015199944A
Publication Date:
February 14, 2020
Filing Date:
October 08, 2015
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K19/00; H03K19/173
Domestic Patent References:
| JP2008085085A | ||||
| JP60021628A | ||||
| JP7131323A | ||||
| JP10056377A | ||||
| JP2011508573A | ||||
| JP2003532188A |
Foreign References:
| US20140159771 |